The present disclosure relates to integrated circuit (IC) chip testing. More particularly, the present disclosure relates to on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support.
Semiconductor integrated circuits are tested after the manufacture to detect malfunctions of the circuits, such as delay faults, stuck-at faults, and transition faults. One known integrated circuit design technique for improving testability is to incorporate test circuits into the circuits to be designed. Such design technique is often referred to as Design-for-Testability (DFT). A popular DFT scheme for integrated circuit (IC) manufacture testing is the scan-based technique. For example, a common method for delivering test data from chip inputs to internal circuits under test (CUTs), and observing their outputs, is called scan-design. In scan-design, registers (flip-flops or latches) in the design are connected in one or more scan chains, which are used to gain access to internal nodes of the chip. Traditionally, the scan chains are comprised of chains of flip-flops (also referred to as “scan flops”) that are used to form serial shift registers for applying input test patterns to combinational logic of the integrated circuit and for reading out the corresponding results. Test patterns are shifted in via the scan chain(s), functional clock signals are pulsed to test the circuit during the “capture cycle(s)”, and the results are then shifted out to chip output pins and compared against expected results. For example, in a typical DFT scan operation, test stimuli are shifted (at relatively slow clock speeds) from an Automatic Test Equipment (ATE) device test channel into the scan chains. Capture clock pulses are then applied on scan flops during capture, and the captured results are then shifted out for analysis.
However, as integrated circuits have become increasingly faster, smaller, and more complex, the spectrum of IC chip defects has grown to include more problems such as high impedance shorts, in-line resistance, and crosstalk between signals, which are not always detected with the traditional static-based tests, known as stuck-at tests. Accordingly, in order to maintain quality levels, it is becoming increasingly necessary to subject ICs to a variety of additional tests that test for different types of faults. As a result, the total amount time required to complete thorough testing of ICs has grown increasing longer.